1.. Field of the Invention
The present invention relates to a semiconductor device having MISFETs and a method for manufacturing the semiconductor device.
2.. Related Art
“Silicon large-scale integrated circuit” is one of the fundamental device technologies that will support the advanced information society in the future. To produce an integrated circuit with highly sophisticated functions, it is necessary to prepare semiconductor devices that yield high performances, such as MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) or CMOSFETs (Complementary MOSFETs) that can constitute an integrated circuit. The performances of devices have been improved basically in accordance with the scaling rule. In recent years, however, it has been difficult to achieve high performances by making devices smaller, due to various physical limitations.
With gate electrodes formed with silicon, there have been such problems as the increasing gate parasitic resistance observed with the higher device operation speed, the decreases of the effective capacitances of insulating films due to the carrier depletion at the interfaces with the insulating films, and the variations in threshold voltage due to the added impurities spreading into the channel regions. To solve those problems, metal gate materials have been suggested.
One of the metal gate electrode forming techniques is a fully-silicided gate electrode technique by which all the gate electrodes are silicided with Ni or Co. To achieve a device operation with an optimum operational threshold voltage, the metal gate electrodes need to have different work functions according to the conductivity types.
This is because the operational threshold voltage of each MIS transistor is modulated with the variation of the gate electrode work function (the effective work function (Φeff)) at the interface between the gate electrode and the gate insulating film. The formation of the gate electrodes having the respective optimum work functions according to the conductivity types complicates the production process of the CMOSFET, and increases the production costs. Therefore, methods for controlling the work function of each electrode through simple procedures are being developed.
For example, when a fully-silicided gate electrode is formed with NiSi, the work function is controlled by depositing another metal at the same time as the Ni deposition (see Y. H. Kim et al., Tech. Dig. IEDM2005, p. 665 (hereinafter referred to as Document 1), and N. Biswas et al., Tech. Dig. IEDM2005, p. 657 (hereinafter referred to as Document 2)).
In the structure disclosed in Document 1, a Ni film and an Al film are formed at the same time, so as to form a fully-silicided gate electrode. By doing so, an Al segregation layer is formed, and a work function of 4.3 eV, which is suitable for an n-type MOS metal on a gate insulating film made of HfO2, is achieved. In the structure disclosed in Document 2, a Ni film and a Ta or Pt film are formed at the same time, so that work functions of 4.2 eV and 4.9 eV, which are suitable for an n-type MOS metal and a p-type MOS metal on a gate insulating film made of SiO2, are achieved. By those simultaneous film forming methods, however, different metal elements are added in accordance with the conductivity types. Therefore, it is necessary to carry out an independent process for forming a full-silicide for each of the conductivity types. This further complicates the production process. In the structure disclosed in Document 1, Al enters the crystal grain boundary of the HfO2 film of a polycrystalline film. This causes in-plane variation in dielectric constant and gate leakage current.
In addition to the technical problems with the structure disclosed in Document 1, the structure disclosed in Document 2 has a work function control range of 0 to 0.2 eV with a high-dielectric film containing Hf, and therefore, can be implemented in very specific circumstances.